The present disclosure relates to a method of fabricating a multi-level metal interconnect for a semiconductor device. Particularly, the disclosure relates to a method of fabricating a damascene metal interconnect.
When an integrated circuit (IC) has gradually increased the number of features that are integrated within it, with a corresponding reduction of a width of metal line, a conventional aluminum interconnect increases its resistance as a result. At the same time, a denser distribution of electrical current usually leads to a more serious electro-migration. As the resistance of the metal interconnects increases, the device suffers from an increase in RC time delay and an increase in capacitance between the metal interconnects. Therefore, the operation speed of the device is reduced. The electro-migration causes a short circuit in the aluminum interconnects. Therefore, copper, which has a lower resistance and exhibits a lower electro-migration, has become a suitable choice for all semiconductor manufacturers. In addition, the copper interconnect can approximately double the operation speed of the device when compared with the aluminum interconnect.
Since copper itself is not easily etched by a conventional etching gas, the fabrication of the copper interconnect cannot be accomplished by the conventional etching method, but is achieved using a damascene technique. The damascene technique involves forming an opening for a metal interconnect, such as a damascene opening in a dielectric layer, followed by filling the damascene opening with metal layers. The metal layers outside the damascene opening are removed by chemical-mechanical polishing (CMP). However, the conventional fabrication method of a copper damascene has technical challenges to overcome.